Gate Driver Design for Si, SiC and IGBT Switches in Modern Power Electronics

Modern insulated gate semiconductor switches such as Si- and SiC-MOSFETs and Si-IGBTs are far easier to use than the bipolar junction transistors and GTO (Gate Turn-Off) thyristors of decades past.

A primary reason is that they are all controlled by a voltage applied to a control terminal—the gate—that looks like a capacitor (albeit a non-linear one). Consequently, the gate only requires current to change states (according to the capacitor equation I = C * [dV / dt]), otherwise these devices act as voltage-controlled current sources, meaning that it’s entirely possible (and quite common, in fact) to drive them from a voltage source with just a resistor in series with the gate to limit the peak current (and dampen any oscillation that might result from the gate capacitance resonating with the omnipresent stray inductance).

Notably missing from the above list of switches is the GaN-HEMT (High Electron Mobility Transistor), because how to drive it very much depends on the device generation and manufacturer, hence I’ll save it for a future article. Otherwise, two assumptions being applied here are that the switches are polarized for positive voltages (i.e. n-type), and that they are normally off (i.e. enhancement mode). That said, the gate voltage levels for fully turning on and off a conventional or “SuperJunction” Si-MOSFET are +10 V and 0 V, respectively, while both the SiC-MOSFET and Si-IGBT benefit from a somewhat higher gate voltage to fully turn on (+15 V is ideal), and will typically require a negative gate voltage to be reliably held off, especially at higher bus voltages and switching speeds (ranging from -3 V to -8 V, depending on the specific device and application).

In less-critical applications it is certainly possible to use the same voltage levels for any of these switch types, with the understanding that overdriving a Si-MOSFET will waste more gate drive power, while underdriving a SiC-MOSFET or Si-IGBT will result in higher conduction losses (though this is often done deliberately to make it easier to protect against shorts using desaturation detection), and not applying a negative bias voltage to the latter types will demand a (potentially dramatic) slowing down of the switching speed to avoid false triggering from the dreaded Miller capacitance (i.e. the capacitance between the drain/collector and the gate).

Other factors that are most important when designing the gate drive circuit are: 1) the placement of the switch in the power converter circuit (i.e. high- or low-side); 2) the peak voltages and currents expected; 3) whether galvanic isolation between the switch and the control circuit is required; 4) the switching frequency; and 5) the total gate charge for the switch.

That last spec—total gate charge, or Q_G—basically lumps together all of the various parasitic capacitances in the switch to give a single value for the quantity of electrons, in coulombs, required per volt of change at the gate.

Note, however, that Q_G also changes—and somewhat non-linearly—with the bus voltage being switched (hence factor #2 above), so the device datasheet will at least give a Q_G for nominal operating conditions, and will often graph out Q_G vs V_GS and Q_G vs. V_DS (or V_CE, for a Si-IGBT). The average power to drive the gate is then found with the straightforward equation: P = Q_G * V_GS * f_sw. For example, a C3M0032120K SiC-MOSFET from Wolfspeed rated at 1,200 V and 63 A max has a Q_G of 118 nC at a V_DS swing of 800 V and a V_GS swing of 19 V (-4 V to +15 V), so if switched at 100 kHz its gate will require (118*E-9) * (19) * (100*E+3) = 0.224 W of drive power.

The two main switch positions are low-side, in which the source or emitter terminal is connected to the negative rail/ground, and high-side, in which the source/emitter is connected to the load. Low-side switches are trivial to drive, and it is entirely possible for the typical switchmode controller IC to directly drive the switch (with the obligatory series gate resistor) in converters operating at moderate power/switching frequency/switch Q_G values. Otherwise, there are myriad specialized gate driver ICs that can pump out much higher peak currents than any controller IC, and that have all sorts of useful features such as Miller clamping, which actively clamps the gate to ground to (sometimes) let you safely use SiC-MOSFETs or Si-IGBTs without a negative supply rail, and overcurrent protection via desaturation detection, which turns off the switch whenever the voltage drop across it exceeds a predetermined value (~7 V is typical, but this can be adjusted downward with a series Zener diode).

Some dedicated gate driver ICs are also capable of driving the switch with bipolar voltages from a logic-level input, and, of course, most will have UVLO, or UnderVoltage LockOut, which ensures that the switch is off whenever the supply voltages are not within range. Basically, the cost/benefit ratio of a modern gate driver IC is hard to pass up in all but the most cost-sensitive of applications.

Driving a high-side (or floating) switch is more of a headache because the gate needs to be more positive than the source/emitter to turn the switch on, but the source/emitter will jump up to the positive supply rail potential when that happens. This is not an uncommon situation, of course, hence there are all sorts of solutions out there. The three main ones are: 1) a small isolation transformer (aka a pulse transformer, aka a GDT, or Gate Drive Transformer); 2) a level-shifting high-side (or half-bridge) driver IC; and 3) a fully isolated gate driver IC.

The first option—a GDT—is very attractive on paper, but can be very difficult to implement in the real world, especially in applications where the duty cycle must span a wide range (or, worse, could/will exceed 50%). This is because transformers demand equal volt-seconds of opposite polarity to reset their core each cycle, so either a DC restoration circuit (which brings its own share of headaches) or a 1:2 primary-to-secondary-turns ratio will be needed so that a 50% duty cycle signal spanning 0 V to +10 V doesn’t get turned into a +/-5 V signal at the switch gate (or a +2 V / -8 V signal at 80% duty cycle, etc). Another critical requirement is that the primary of the GDT must always be driven with a low impedance (which also implies that the GDT must have very low leakage inductance), otherwise the switch could partially turn on when it is supposed to be off, or even start oscillating, both of which are no bueno. Given the other gate drive options available these days, GDTs are best reserved for topologies that always drive their switches at 50% duty (e.g. the phase-shifted full bridge) and/or when a really high isolation voltage rating is required (e.g. >7.5 kV).

Another solution that is very tempting for both cost and circuit complexity reasons is the use of level-shifting high-side and half-bridge driver ICs, exemplified by the legendary (or infamous) International Rectifier (now Infineon) IR2110. These ICs are fabricated on high-voltage processes rated for 600 V or more to allow level-shifting a logic level control signal up to a high-side switch, and to avoid needing an isolated supply to drive said switch, they typically use a so-called “bootstrap” charge pump to store +10 V to +15 V in a small capacitor every time the low-side switch turns on. The lack of galvanic isolation is an obvious downside—a catastrophic failure on the power side probably won’t stop there—but a more subtle gotcha is that these ICs also have a limited duty cycle and frequency range when using the bootstrap charge pump because the low-side switch must turn on for some minimum amount of time, and when the high-side switch is off, to recharge the bootstrap capacitor, while said capacitor can only power the high-side circuit for so long.

Also pay close attention to the dV/dt transient immunity spec, as failing to respect this (by attempting to switch too quickly) can result in latchup failure, which is exactly as bad as it sounds. Still, these ICs are a compelling option for cost-sensitive and/or “everyday” power conversion applications, particularly when the load itself is isolated (as well as any feedback paths, if required).

Finally, there are gate-drive isolator ICs, which combine the peak current rating and rich feature set of a low-side or half-bridge gate driver with true galvanic isolation, all in a conventional IC package. Pretty much all of these ICs can operate from 0-100% duty (so there’s no lower limit on frequency, as with GDTs and bootstrapped level-shift drivers), and will have sufficient dV/dt immunity (called Common Mode Transient Immunity, or CMTI, when applied to isolators) for typical EV applications. Many of them will also have safety agency approval/listing, which is a definite plus compared to, say, a bespoke GDT whipped up in the lab with an off-the-shelf toroidal core and some wire wrap wire (c’mon, we’ve all done this…or maybe I’m just showing my age).

The main isolation techniques used in these ICs are optical, magnetic and capacitive. Optical types use a conventional LED and photodiode (or, rarely, phototransistor) optocoupler for isolation, and while they’ve been around the longest, they are not necessarily the cheapest option. Optical isolators also have a relatively low upper frequency limit, due to minority carrier recombination in the photodiode or phototransistor, and typically, a relatively low CMTI compared to the magnetic and capacitive types. Magnetic isolators use an IC-scale, coreless transformer composed of two spiral coils separated by an insulator (e.g. SiO₂) for isolation, while in the capacitive types the forward and return current pathways between the input and output sides are bridged with…yes, capacitors. Both magnetic and capacitive isolators convey pulse information across the isolation boundary by modulating an RF carrier signal (typically using burst, or on/off, modulation) to enable operation down to DC and up to some fraction of half the carrier frequency (i.e. less than the Nyquist limit). Both types can achieve extremely high CMTI ratings (100 V/ns or better) and can theoretically transmit power across their isolation barriers to power their output sides, but I’m only aware of this latter feature in a select few magnetic isolators from Analog Devices (e.g. the ADuM5230, which can supply a whopping 150 mW). Frankly, the optical, magnetic and capacitive isolators are more or less functionally similar, but capacitive types are often the least expensive.

Finally, whenever two or more switches are paralleled to achieve a higher current rating, it’s obvious that gate-drive power will increase monotonically with switch count, so at some point it will make sense to use individual drivers for each switch, rather than a single driver (and individual series gate resistors, as per usual). A more subtle issue with paralleled switches is unequal current sharing due to inevitable differences in voltage drop (whether from R_DS[on] or V_CE[sat]), transconductance, threshold voltage, etc. One can progressively derate the total array current to (hopefully) prevent any one switch experiencing overcurrent, but another solution frequently touted is so-called active (or adaptive) gate drive, in which (most commonly) a central controller monitors the current through each switch and then adjusts their individual gate voltages (and even their timing) on the fly. As you might imagine, active gate drive can get awfully complicated awfully quick, hence it rarely compares favorably with just slapping in another switch or two and calling it a day.

This article first appeared in Issue 76 – Subscribe now.